Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Non-volatile memory is memory that can retain its data values for some extended period without the application of power. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Changes in threshold voltage of the cells, through programming (which is sometimes referred to as writing) of charge-storage structures (e.g., floating gates or charge traps) or other physical phenomena (e.g., phase change or polarization), determine the data value of each cell. Common uses for flash memory and other non-volatile memory include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile telephones, and removable memory modules, and the uses for non-volatile memory continue to expand.
A NAND flash memory device is a common type of flash memory device, so called for the logical form in which the basic memory cell configuration is arranged. Typically, the array of memory cells for NAND flash memory devices is arranged such that the control gate of each memory cell of a row of the array is connected together to form an access line, such as a word line. Columns of the array include strings (often termed NAND strings) of memory cells connected together in series, source to drain, between a pair of select lines, a source select line and a drain select line.
A “column” refers to a group of memory cells that are commonly coupled to a local data line, such as a local bit line. It does not require any particular orientation or linear relationship, but instead refers to the logical relationship between memory cell and data line. The source select line includes a source select gate at each intersection between a NAND string and the source select line, and the drain select line includes a drain select gate at each intersection between a NAND string and the drain select line. Each source select gate is connected to a source line, while each drain select gate is connected to a data line, such as column bit line.
In order for memory manufacturers to remain competitive, memory designers are constantly trying to increase the density of memory devices. Increasing the density of a flash memory device generally requires reducing spacing between memory cells and/or making memory cells smaller. Smaller dimensions of some device elements may cause operational problems with the cell. For example, the channel between the source/drain regions becomes shorter, possibly causing severe short channel effects.
One way of increasing the density of memory devices is to form stacked memory arrays, e.g., often referred to as three-dimensional memory arrays. For example, one type of three-dimensional memory array may include pillars of stacked memory elements, such as substantially vertical NAND strings.
FIG. 1A presents an example of a portion of a memory array 100 of the prior art that includes substantially vertical strings of memory cells 110 located adjacent to substantially vertical semiconductor pillars 120 that may act as channel regions for the strings of memory cells located thereon. That is, during operation of one or more memory cells 110 of a string, a channel can be formed in the corresponding semiconductor pillar 120.
FIGS. 1B and 1C respectively show cross-sections of memory cells 110T and 110B located at different levels (e.g., vertical levels) within memory array 100. For example, memory cell 110T is located at a vertical level (e.g., near the top of memory array 100) that is above a vertical level (e.g., near the bottom of memory array 100) at which memory cell 110B is located.
Semiconductor pillars 120 may be tapered in a direction from top to bottom, causing the radius of semiconductor pillars 120 to be smaller at memory cell 110B near the bottom of memory array 100 than at memory cell 110T near the top of memory array 100, as shown in FIGS. 1A-1C. Charge-storage structures 130 are located adjacent to semiconductor pillars 120 and may also be tapered in a direction from top to bottom. The radius of charge-storage structure 130 may be smaller at memory cell 110B than at memory cell 110T. Memory cells 110 may include a control gate 140 (e.g., as a portion of or coupled to an access line, such as a word line) located adjacent to a respective charge-storage structure 130.
Semiconductor pillars 120 and charge-storage structures 130 are sometimes formed in openings formed though a material, such as alternating dielectrics and conductors, e.g., that form the control gates 140, and therefore take on the overall shape of the openings. In some instances, the process, e.g., etching, that forms these openings results in openings that taper in a direction from top to bottom, thereby causing a semiconductor pillar 120 and a charge-storage structure 130 formed therein to be tapered as shown.
The difference in the radius of the pillar 120 at memory cells 110T and 110B and/or the difference in the radius of the charge-storage structure 130 at memory cells 110T and 110B can cause differences in the programming properties of memory cells 110T and 110B. This means that the programming properties of the memory cells may vary over the height of the string of memory cells. For example, the larger radius of the pillar 120 at memory cell 110T and/or the larger radius of the charge-storage structure 130 at memory cell 110T may cause memory cell 110T to program more slowly than memory cell 110B. This is due in part to the reduced gate coupling ratio associated with the larger radius of the pillar 120 at memory cell 110T and/or the larger radius of the charge-storage structure 130 at memory cell 110T, where the gate coupling ratio may be defined as the ratio of the voltage imparted to the charge-storage structure 130 during programming to the voltage applied to control gate 140 during programming.
In addition, the cell-to-cell interference between adjacent memory cells, due to the capacitive coupling (e.g., termed parasitic capacitance) between the adjacent memory cells, may be larger at memory cell 110T than at memory cell 110B, e.g., owing to the larger radius of the pillar 120 at memory cell 110T and/or the larger radius of the charge-storage structure 130 at memory cell 110T. The cell-to-cell interference may also act to reduce the gate coupling ratio.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternatives to existing memory arrays with pillars of stacked memory elements.